Cadence Design teams with TSMC to accelerate design of AI silicon

Cadence (CDNS) announced an expansion of its relationship with TSMC (TSM) to accelerate AI-driven semiconductor innovation. The expanded collaboration will deliver IP, signoff-ready, end-to-end design infrastructure, and advanced, certified flows for AI silicon on TSMC’s N3, N2, A16 and A14 process technologies. The companies’ said enhanced work will help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs-accelerating time to silicon with greater confidence. “AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures,” said Chin-Chi Teng, senior vice president and general manager, Cadence. “Through collaboration with TSMC, we’re advancing our Design for AI and AI for Design strategy by uniting certified flows with silicon-proven IP and building the agent-ready foundation that will help engineers improve productivity as complexity continues to rise.”