Speedata Highlights RISC-V-Based Analytics Architecture at World RISC-V Days 2026

A LinkedIn post from Speedata indicates the company will present at World RISC-V Days 2026 in Tel Aviv on Sunday, February 22. The session, led by Software Team Leader Omri Mezrich, is set to address how RISC-V is being adopted within Speedata’s analytics processing unit (APU) architecture.

According to the post, the presentation will cover the rationale for choosing RISC-V, integration of RISC-V cores in a heterogeneous compute architecture, and a firmware-focused deep dive on C++ and asynchronous programming for high throughput under tight resource constraints. For investors, the content suggests an emphasis on open, customizable architectures and software efficiency, which could be relevant for cost-performance differentiation in data analytics, AI, and ETL workloads.

The company’s participation in an event organized by RISC-V International and hosted at Bar-Ilan University may also signal ongoing engagement with the open hardware ecosystem and the local Israeli semiconductor and AI community. Such visibility could help Speedata position its APU technology within emerging RISC-V–based infrastructure and potentially attract ecosystem partners, technical talent, and future commercial collaborations.