Speedata Explores AI-Driven VLSI Verification Methodology

According to a recent LinkedIn post from Speedata, the company is experimenting with integrating AI into VLSI verification workflows using a low‑risk UART‑to‑AXI bridge as a test vehicle. The post highlights that simply directing AI tools at a code repository was not effective without a structured methodology capturing internal verification standards.

The company’s LinkedIn post describes a Markdown‑based guide that encodes practices such as UVM layering, directory structure, scoreboard completion criteria, and synchronization handling, enabling AI to generate scaffolding and keep documentation aligned while engineers retain sign‑off control. The result, according to the post, was a structured test ladder focused on end‑to‑end correlation, including sanity, back‑to‑back, and data‑integrity tests.

For investors, the post suggests Speedata is investing in process innovation around AI‑assisted chip verification, an area that could reduce verification time and engineering overhead if successfully scaled. Such efficiencies may improve time‑to‑market for complex semiconductor designs and potentially enhance margins, while also positioning the company as an early adopter of AI‑driven verification methodologies in the semiconductor design ecosystem.