According to a recent LinkedIn post from Speedata, the company is exploring ways to integrate AI into very-large-scale integration (VLSI) verification while maintaining engineering control over verification intent. The post describes work led by Speedata’s internal AI specialist using a UART-to-AXI bridge as a low-risk pilot block to validate AI-assisted workflows before applying them to more complex designs.
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The post indicates that Speedata developed a Markdown-based methodology guide that encodes internal standards such as UVM component layering, directory structures, scoreboard definitions, and synchronization practices. This structured approach is presented as enabling AI tools to generate scaffolding, propagate specification changes across files, and keep documentation aligned, while engineers retain final responsibility for verification decisions and sign-off.
According to the description, the pilot produced a structured test ladder focused on end-to-end correlation, including sanity, back-to-back, and data-integrity tests designed to validate routing decisions without unwanted state interactions across ports. The post suggests that the broader lesson for the company is that AI may be most effective in accelerating routine aspects of verification, such as scaffolding and consistency, rather than replacing core engineering judgment.
For investors, this emphasis on AI-assisted verification could signal an effort by Speedata to increase verification productivity and reduce development cycles in complex semiconductor projects. If successfully scaled, such internal methodologies may improve time-to-market and design quality, potentially enhancing the company’s competitive position in AI-focused chip design and verification-intensive markets.