Normal Computing Raises $50 Million to Advance AI-Native Chip Design and Thermodynamic Computing

New updates have been reported about Normal Computing.

Normal Computing has secured $50 million in new strategic capital led by Samsung Catalyst Fund, lifting total funding above $85 million and reinforcing its position as an AI-native EDA and semiconductor innovation platform. The company is using this funding to scale its Normal EDA software, expand partnerships with leading chipmakers, and accelerate development of its physics-based Carnot hardware program, with a focus on improving intelligence per dollar and per watt as data centers near an energy ceiling.

Normal EDA applies AI and auto-formalization—combining large language models with formal logic—to automate and verify complex silicon design workflows, aiming to cut custom chip design cycles from years to months while improving first-silicon success. In parallel, Normal is advancing its CN101 thermodynamic computing chip, a physics-based ASIC targeting multimodal diffusion GenAI inference, with a roadmap that aims for up to 1,000x energy-efficiency gains versus conventional architectures that fight, rather than exploit, physical randomness.

The company reports that it already works with more than half of the world’s top ten semiconductor companies by revenue, positioning its platform at the center of efforts to address escalating chip complexity, talent constraints, and mounting AI compute energy demands. CEO Faris Sbahi frames the strategy as unifying design methodology and novel hardware architectures to reshape AI scaling economics, arguing that incremental efficiency improvements will be insufficient as data centers approach an energy wall around 2030.

The round brings in new investors including Galvanize, Brevan Howard Macro Venture Fund, and ArcTern Ventures, alongside returning backers such as Celesta Capital, Drive Capital, First Spark Ventures, and Micron Ventures, signaling growing institutional confidence in Normal’s approach. Samsung Catalyst Fund’s leadership of the financing underscores strategic alignment with major ecosystem players that want faster time-to-market for leading-edge custom silicon, while validating Normal’s team and platform as credible production tools rather than experimental R&D.

Normal’s Carnot program and CN101 chip are partly funded by the U.K.’s Advanced Research + Invention Agency through its Scaling Compute Programme, highlighting government interest in non-incremental compute architectures capable of transformative gains. ARIA’s involvement reflects recognition that thermodynamic and physics-based computing could materially alter the cost structure and energy profile of AI workloads such as image and video generation, creating potential downstream impact for cloud providers, hyperscalers, and enterprise AI users.

Strategically, this funding round gives Normal additional runway to deepen its EDA product suite across DV, RTL automation, and emerging end-to-end design flows, while also using its own tools internally to generate hardware IP that can showcase and stress-test its platform. The company also supports open EDA standards and is a founding member of the Silicon Integration Initiative LLM Benchmarking Coalition, which may help shape industry metrics for AI-assisted chip design and lock in Normal’s methodologies as reference points.

For executives in the semiconductor and AI infrastructure markets, Normal’s trajectory suggests a potential shift toward AI-native design stacks that integrate deeply with engineering workflows and co-evolve with new compute architectures. If Normal delivers on its roadmap, the combination of accelerated design cycles, higher design success rates, and orders-of-magnitude energy efficiency improvements could materially affect capex and opex assumptions for next-generation AI hardware deployments.

Headquartered in New York with offices in San Francisco, London, and Copenhagen, Normal is building a team drawn from major technology and semiconductor firms and national labs to execute on this dual software-hardware strategy. The company’s bet is that controlling both the AI EDA layer and a new class of physics-based chips will allow it to capture value across the semiconductor stack, as industry stakeholders seek solutions to the combined challenges of AI scaling, energy constraints, and increasing design complexity.